1. Field of the Invention
The present invention relates generally to data processing systems employing bussed architectures and more particularly relates to such systems having multiple memory busses.
2. Description of the Prior Art
It is known in the art that busses reduce the number of components over straight point-to-point interconnections, because various components are time shared. However, as a result of this time sharing, the transfer speed of the bus becomes significant as a potential limiting factor with regard to system performance.
The factors involved in high performance bus designs are primarily related to the basic physics of electronic information transfer. Most especially these include bus length, power dissipation, distributed capacitance, number of bus connections, various “tuning” characteristics, etc.
Oftentimes, these factors act at cross purposes. For example, increased spacing of bussed components decreases performance. In compensation therefore, greater transfer energies can be utilized. However, such increased transfer energy generates more heat which needs to be dissipated. A primary method of increasing heat dissipation capacity is through the increase of bus component spacing. Those of skill in the art will readily appreciate many other interrelationships of the various design factors.
Quite often larger scale systems benefit from architectures having multiple busses. This is particularly the case for systems having multiple instruction processors, multiple input/output processors, and multiple component hierarchical memory structures.
Because of the disparate natures of these different system components, the associated bussing designs have differing characteristics. For example, the various busses may have different transfer rates, different widths (i.e., number of independent bit positions), different control protocols, etc. As a result, optimization of multiple busses within a given system tends to be extremely difficult.